Here are the data structures with brief descriptions:

[detail level 123]

▼N__cxxabiv1
Ccxaguard
▼NArch
Cstackframe
▼NBoot
Cargument
CHandoff
CHandoffCPUDescriptor
CHandoffRSDPDescriptor
CHandoffSMPDescriptor
▼NGDT
▼CBase
CBaseSections
CEntry	GDT Code & Data Segment Selector Struct See https://wiki.osdev.org/Descriptors#Code.2FData_Segment_Descriptors for details
▼CLimit
CLimitSections
▼NGraphics
CFramebuffer
▼NIDT
CGate
▼COffset
COffsetSections
CSegment
▼NLinkedList
CLinkedList
CLinkedListNode
▼NMemory
▼NPhysical
CPhysicalManager
CMemoryMap
CSection
▼NTime
CTimeDescriptor
CBitset
CCR0
CCR2
CCR3
CDirectory	Page directory contains pointers to all of the virtual memory addresses for the page tables along with their corresponding physical memory locations of the page tables. Page table entry defined in accordance to the Intel Developer Manual Vol. 3a p. 4-12
CDirectoryEntry	Page directory entry structure as defined in accordance to the Intel Developer Manual Vol. 3a p. 4-12
CFrame	Page frame structure. This represents a the address to a single unit of memory in RAM. (Chunk of physical memory)
CGDTR
CIDTR
CLogger
CMutex
CPage	Virtual address structure. Represents an address in virtual memory that redirects to a physical page frame. (Chunk of virtual memory)
CRAIIMutex
Cregisters	A structure definining values for all x86 registers. Cannot be namespaced due to C linkage and ASM interoperability
CRingBuffer
CSemaphore
CTable	Page table structure as defined in accordance to the Intel Developer Manual Vol. 3a p. 4-12
CTableEntry	Page table entry defined in accordance to the Intel Developer Manual Vol. 3a p. 4-12
Ctask
Ctask_sync
Ctasklist
Ctss_entry	The Task State Segment (TSS) is a special data structure for x86 processors which holds information about a task. The TSS is primarily suited for hardware multitasking, where each individual process has its own TSS. In Software multitasking, one or two TSS's are also generally used, as they allow for entering Ring 0 code after an interrupt. (OSDev Wiki)